With DRAM, at a very basic level each cell is a capacitor that holds a certain amount of charge, much like a bucket holds water. If the bucket is full, it represents a 1. If the bucket is below the half way point or empty, it represents a 0.

If you have ever played chess before, you may have seen people refer to the squares on a chess board in code – such as C4, where C is the column and 4 is the row. In a similar way, you can access a memory cell for reading or writing, except you won’t use letters, you will use a numbered memory address. If this method was used for every single cell in a stick of memory, this would require a lot of wiring and this would increase costs considerably. DRAM gets around this by having a common unit that can address all the rows and another common unit that can address all the columns. Imagine this being like those games you play at the fair ground where you try and catch the cuddly toy with the claw. First you choose your row by moving left or right, then finally choose your column by moving forward or back.

As you can see above, having a decoder unit for selecting the correct column and row reduces wiring considerably. The down side of this, it is introduces latency in accessing the cells for reading or writing.

Latencies Explained

The latencies introduced by this system are known as the CAS Latency (Column Access Select) and RAS to CAS Delay (Row Access Select) or tCL and tRCD. Of these, the CAS latency has the most impact on performance, as data is usually stored sequentially in a row. For instance, in a lot of cases, the computer will be selecting 8bits at a time to select a whole byte. To do this requires one row select and 8 column selects – that is quite a ratio.

Going back to the bucket example, imagine these buckets have holes in the bottom and slowly leak out water. This introduces yet another problem. To combat this, the capacitors in the cells have to be regularly refreshed, or in the case of a bucket, simply topped up. If the charge/water of a cell holding the value 1 drops below the half way point, the computer won’t know if it was meant to be a 1 or a 0. This is why this refreshing has to be done regularly and quickly in order to keep the data consistent. This unfortunately also introduces another latency called RAS Precharge or tRP.

The final delay that is usually referenced to is the Cycle Time (tRAS), which is how long it takes for the pins to receive a signal and the row to start being selected. The row is always selected before the column.

When you are buying memory, you may see latencies referenced to in 2 ways. One such way is 3-4-4-8. This in order of tCL-tRCD-tRP-tRAS, as described above. The other way is simply C3, CL3 or CAS3. The reason some manufacturers choose the simpler method, is because as explained above – the CAS latency is by far the most important value. Latencies describe delay in clock cycles, so it is important to remember that a lower value is better.

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